1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Art
In planar MOSFETS, stress induced carrier mobility enhancement techniques have been developed. On the other hand, FinFET (one of the double gate transistors) has been developed for CMOS scaling, low power operation and high performance.
However, non-planar device, such as FinFET or multiple-gate device, has different structure of the gate electrode and the channel region and channel orientation from those of planar MOSFET. Therefore, the method of applying stress effectively for carrier mobility enhancement is different from that of planar MOSFET. Furthermore, stress sensitivities of channel orientation for nMOSFET and pMOSFET are different from each other.
In planar CMOSFETs, technique of applying different direction of stress in fins of nMOSFET and pMOSFET from each other has been demonstrated to enhance carrier mobility of both nMOSFET and pMOSFET. For example, tensile SiN liner for nMOSFET and compressive SiN liner for pMOSFET have been used. This case, however, had the problem that the manufacturing process becomes complex, and the problem that the tensile and compressive stress can be canceled out in adjacent nMOSFET and pMOSFET. (see Scott E. Thompson et al. “In Search of “Forever”, Continued Transistor Scaling One New Material at a Time” IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, February 2005).